The present invention relates to timing of pulse transitions, and more particularly to a variable transition time generator for providing continuous and independently controllable transition times for both edges of pulses.
Control of pulse transitions is frequently a necessary function of pulse sources in test and measurement equipment. For example the output transition times of logic device characterization instruments must be matched to the characteristics and test specifications of devices or systems under test. The minimum output transition times and propagation delays of the circuit need to be as short as possible, comparable to the transition times of the logic being tested, which are likely to be comparable to logic fabricated with the same technology as the control circuit. Transition times must be continuously and independently controllable over at least a decade (10:1) range. Typical high speed logic testing equipment requires controlling a large number of output signals simultaneously, using many control circuits in parallel, so that simplicity and low power and cost in each signal path is necessary.
The requirements in terms of speed and scale, as well as cost, dictate integration to as large a degree as possible, as opposed to discrete or multichip per pin solutions. The needed speed, precision and integration density tend to favor a modern silicon bipolar process, although with suitable adjustments other devices than bipolar transistors, such as FETs, or other processes, such as GaAs, may also be used.
A typical prior art pulse transition time control circuit used in slower applications is shown in FIG. 1. When the control input Vin is negative, the positive timing current Itp flows through QP1, and the negative timing current Itn through QN2 and the clamping diode DN, holding the output Vo at the level set by the negative clamp voltage Vnc. When Vin switches positive, QN2 is turned off by QN1 and Itp is switched to QP2, charging the timing capacitor Ct positively until the positive clamping diode DP turns on and holds the output as determined by Vpc. The process is reversed when Vin again switches negative. To achieve a fast minimum transition time Ct needs to be as small as possible. Therefore a buffer amplifier Ao is usually included between the resulting high impedance timing node and the ultimate output Vout of the circuit. Many variations and elaborations of this circuit with respect to switching QP2 and QN2, output clamping arrangements and other aspects exist. All of these variations can provide independent control of the positive and negative output transitions by controlling Itp and Itn.
In the context of fast IC processes these circuits have serious drawbacks. A PNP device QP2 is needed. The fastest available PNPs in complementary processes are much slower than the NPNs and seriously degrade the speed of the circuit. The controllable pull-up current source Itp is also difficult to make using NPNs only. The power supply voltages needed are likely to exceed those available in a logic environment. Also a multichip solution is undesirable, as noted above.
What is desired is a high speed variable transition time generator that uses NPN devices only to provide high speed on a single chip while using available logic power supply voltages.